Researchers Develop RISC-V Chip for Quantum-Resistant Encryption

(TomsHardware) A research team with the Technical University of Munich (TUM) have designed a quantum cryptography chip aimed at the security demands of the quantum computing revolution. The RISC-V chip, which was already sent to manufacturing according to the researchers’ design, aims to be a working proof of concept for protecting systems against quantum computing-based attacks, which are generally considered to be one of the most important security frontiers of the future. Alongside the RISC-V based hardware implementation (which includes ASIC and FPGA structures), the researchers also developed 29 additional instructions for the architecture that enable the required workloads to be correctly processed on-chip.

NOTE: RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

To fill the void of information on this novel security exploit, the TUM researchers have also fitted their chip with four distinct hardware Trojans. These will literally destroy their proof-of-concept chip layer by layer while feeding each step of the process to newly-developed machine learning algorithms, training them in identifying hardware functions even in the absence of technical information regarding what the hardware does exactly. This helps to identify components (Trojans) that perform functions unrelated to the chip’s actual tasks that may have made their way into the final design. This research will also likely provide lasting effects in the reverse-engineering space, and it’s likely that it’s being pursued by other parties (academic or otherwise).
In designing their quantum-security chip, the TUM researchers took a cohesive (and world first) hardware and software co-design approach, with purpose-designed hardware that accelerates the current poster-child for quantum cryptography, the lattice-based Kyber algorithm. The researchers say they’ve achieved a 10x performance increase compared to current software Kyber encryption solutions, while using around eight times less energy.